
Table 3-11:
R
Ethernet PHY Daughtercard J16 Connection
Ethernet PHY Daughtercard Support
J16-EVEN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J16-ODD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal
No connect
P1_RXC_RXCLK (3)
P1_RD_RXD1
P1_RXCTL_RXDV
P1_RCLK1 (4)
P1_CRS
P1_RXER
P1_RXD7
P1_RD_RXD0
No connect
P1_RD_RXD2
P1_RD_RXD3
P1_RXD4
P1_RXD5
P1_RXD6
P0_CRS
No connect
P0_RD_RXD0
P0_RD_RXD1
No connect
P0_RD_RXD2
No connect
P0_RXCTL_RXDV
P0_RXD4
P0_RXD5
P0_RXD6
P0_RXD7
P0_RCLK1 (4)
P0_RD_RXD3
P0_RXER
P0_RXC_RXCLK (3)
No connect
FPGA Pin (1)
J10
E11
M10
K18
G11
G12
E6
T9
G6
T10
F5
R9
H5
R11
M6
N8
M7
J6
P5
L5
P6
K6
H14
J5
R8
H7
NC (2)
NC
NC
NC
NC
NC
FPGA In/Out
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
Notes:
1. These signals are connected to FPGA banks 12 and 20. The bank reference voltage, V CCO , is 2.5V. See the ML555 board schematics
on the CD-ROM for additional information.
2. NC = no connect.
3. These clocks are connected to FPGA clock-capable I/O pins.
4. These clocks are connected to FPGA global clock pins.
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
43